Most telecom/datacom systems are implemented with a number of digital/mixed signal integrated circuits (ICs), which require an accurate and stable clock source for normal operations. This clock is typically generated by a digital phase-locked loop (DPLL), which receives a recovered reference clock from a network port, cleans it from jitter and wander, and then synthesizes the frequencies required by different integrated circuits in the system. When the input reference clock is unavailable, the DPLL may also be operated in the free-run mode, wherein it continues to run without an input reference.
The DPLL requires a stable master clock, which is generated from an external crystal oscillator (XO) or temperature compensated variants, such as a temperature compensated crystal oscillator (TCXO) or an oven controlled crystal oscillator (OCXO).
In the case of master clock failure, the DPLL will instantly stop generating an output clock and the whole system will fail. XOs typically have a higher failure rate than ICs, and as such can dominate the overall failure rate of the whole system.